Ace Your Digital Logic Exam: Chapter-Wise Past Year Questions for CSIT First Semester
Welcome, CSIT first-semester students! Preparing for your Digital Logic exam? You've come to the right place. This post provides a chapter-wise compilation of important questions from past years to help you focus your studies and boost your exam preparation.
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Chapter 1: Binary Systems
Explore fundamental concepts of binary systems with these past year's questions:
- Convert the following decimal number into hexadecimal and octal:
- 334
- 225
- Convert the hexadecimal number 2BFC to binary and then to octal. (Year: 2071, Group B, Marks: 5)
- Convert 3EC8₁₆ into different numbering systems that you know. (Year: 2071, Group A, Marks: 10)
- What are the various types of numbering systems used in digital logic? Explain. (Year: 2071, Group A, Marks: 10)
- Convert the following:
- A08E.FA₁₆ = (?)₁₀
- AE9.B0E₁₆ = (?)₂
- Convert the following hexadecimal number to decimal and octal numbers:
- 4FF
- 6FED
- Perform the arithmetic operation (+42)+(-13) and (-42)-(-13) in binary using the signed 2’s-complement representation for negative numbers. (Year: 2074, Group B, Marks: 5)
- Represent decimal number 4673 in:
- octal
- BCD
- Represent -6 (negative six) using 8 bits in signed magnitude, signed-1 ''s-complement, and signed-2 ''s-complement, respectively. (Year: 2077, Group B, Marks: 5)
- List two major characteristics of digital computers. (Year: 2077, Group B, Marks: 5)
- Represent the decimal number 0.125 into its binary form. (Year: 2078, Group B, Marks: 5)
- Perform 1's complement subtraction: 110101 - 100101. (Year: 2078, Group B, Marks: 5)
- Perform the following operations:
- (011101)₂ - (110011)₂ using 2's complement
- (89344)₁₀ - (98654)₁₀ using 9's complement
- Given A=46 and B=35, represent them in binary and perform A-B using 1’s complement method. (Year: 2081, Group B, Marks: 5)
- Explain the error detection code with example. (Year: 2073, Group B, Marks: 5)
- What do you mean by the Gray code? What are its applications? (Year: 2072, Group B, Marks: 5)
- Write short notes on: Error detection codes (Year: 2081, Group B, Marks: 5)
Chapter 2: Boolean Algebra and Logic Gates
Master Boolean algebra and logic gates with these important questions:
- Proof the De-Morgan 1st and 2nd theorem with truth table and logic gates. (Year: 2071, Group B, Marks: 5)
- Simplify the Boolean expression: Y = A̅B̅ + A̅ + B̅. Prepare truth table to show that the simplified expression is correct or not. (Year: 2071, Group B, Marks: 5)
- Write short notes on: Universal gates (Year: 2071, Group B, Marks: 5)
- Write short notes on: CMOS (Year: 2071, Group B, Marks: 5)
- State and prove commutative laws, associative laws, and distributive law using logic gates and truth table. (Year: 2072, Group B, Marks: 5)
- Prove that:
- A̅B̅C̅((A̅+B̅+C̅)) = A̅B̅C̅
- A + B̅C(A + B̅C) = A
- Show that both NAND gate and NOR gate are universal gates. (Year: 2072, Group B, Marks: 5)
- What do you mean by the Gray code? What are its applications? (Year: 2072, Group B, Marks: 5)
- Explain the duality theorem with example. (Year: 2073, Group B, Marks: 5)
- Write short notes on: De-Morgan's theorem (Year: 2074, Group B, Marks: 5)
- Express the complement of the following function in sum of minterms: F(A,B,C,D) = Σ(0,2,6,11,13,14) (Year: 2074, Group B, Marks: 5)
- Write short notes on: TTL (Year: 2074, Group B, Marks: 5)
- Express the Boolean function F = A + B'C in a sum of minterms. (Year: 2075, Group B, Marks: 5)
- Show that the positive logic NAND gate is a negative logic NOR gate and vice versa. (Year: 2077, Group B, Marks: 5)
- Where is CMOS suitable to use? Define Power dissipation. (Year: 2077, Group B, Marks: 5)
- Write short notes on: RTL (Year: 2077, Group B, Marks: 5)
- Write short notes on: POS (Year: 2077, Group B, Marks: 5)
- Express the Boolean function F = x + yz as product of max-terms. (Year: 2078, Group B, Marks: 5)
- Write short notes on: CMOS (Year: 2078, Group B, Marks: 5)
- Write short notes on: Negative Logic (Year: 2078, Group B, Marks: 5)
- Explain De-Morgan’s Law. (Year: 2081, Group A, Marks: 10)
Chapter 3: Simplification of Boolean Functions
Practice simplifying Boolean functions using K-maps with these questions:
- Explain the K-map with three variables. (Year: 2070, Group B, Marks: 5)
- Simplify the following Boolean function using three-variable K-map:
- F(X,Y,Z) = Σ(0,3,2,5)
- F(A,B,C) = Σ(0,2,4,5,6)
- Reduce the following expression using K-map:
- (A+B)(A+B'+C)(A+C')
- A + B(A + B' + D)(B + C')(B + C + D)
- Reduce the following function using K-map: F = wxy + yz + xy’z + x’y (Year: 2074, Group B, Marks: 5)
- Reduce the following function using K-map: F = B'D + A'BC' + AB'C + ABC' (Year: 2075, Group B, Marks: 5)
- Minimize the Boolean function using K-map: F(A,B,C,D) = Σ(0,1,3,5,7,8,9,11,13,15) (Year: 2078, Group B, Marks: 5)
- If f(P,Q,R,S) = Σ(3,4,7,8,14) and d(P,Q,R,S) = Σ(1,6,9,13), simplify using K-map and design the circuit using minimum number of NAND gates. (Year: 2080, Group B, Marks: 5)
- Simplify F(A,B,C,D) = Σ(1,3,4,6,9,11,12,14) and realize the equation using NOR gates only. (Year: 2081, Group B, Marks: 5)
- Simplify the Boolean function F(P,Q,R,S) = Π(0,1,4,5,11,14,15) and d(P,Q,R,S) = Σ(2,3,7,8,9,13) using K-map in both SOP and POS form. (Year: 2081, Group A, Marks: 10)
Chapter 4: Combinational Logic
Practice designing combinational logic circuits with these past exam questions:
- Design a half adder logic using only NAND gates. (Year: 2070, Group B, Marks: 5)
- Design Magnitude comparator and also design a logic diagram for a 4-bit magnitude comparator. (Year: 2070, Group A, Marks: 10)
- Explain the combination logic with examples. (Year: 2070, Group B, Marks: 5)
- Design a magnitude comparator using logic gates and truth table. (Year: 2072, Group A, Marks: 10)
- Design a 4 input multiplexer using logic diagram and truth table. (Year: 2072, Group B, Marks: 5)
- Design half adder logic circuit using only universal gates. (Year: 2073, Group B, Marks: 5)
- Design a combinational circuit with three inputs and six outputs. The output binary number should be the square of the input binary number. (Year: 2074, Group B, Marks: 5)
- Design a combinational circuit with three inputs and one output. The output is 1 when the binary value of the inputs is an odd number. (Year: 2078, Group B, Marks: 5)
- Design a combinational circuit with three inputs, x, y, and z, and three outputs, A, B, and C. When the binary input is 0, 1, 2, or 3, the binary output is one greater than the input. When the binary input is 4, 5, 6, or 7, the binary output is one less than the input. (Year: 2075, Group B, Marks: 5; 2081, Group A, Marks: 10)
- Design a full subtractor circuit with three inputs x, y, Bin and two outputs Diff and Bout. (Year: 2077, Group B, Marks: 5)
- Design a combinatorial circuit that generates 9's complement of a BCD number. (Year: 2077, Group A, Marks: 10)
- Design 4-bit even parity generator. (Year: 2077, Group B, Marks: 5)
- Derive the Boolean expression for sum and carry of half adder. Draw its combinational circuit. Implement it using only NAND gates. (Year: 2078, Group B, Marks: 5)
- Explain 4-bit magnitude comparator. (Year: 2078, Group B, Marks: 5)
- What is combinational circuit? Design a combinational circuit with four inputs that represent a decimal digit in BCD and four output lines that generate the 1's complement of the input binary patterns. (Year: 2080, Group A, Marks: 10)
- Design a full subtractor with necessary tables and logic diagram. (Year: 2080, Group B, Marks: 5)
Chapter 5: Combinational Logic with MSI and LSI
Explore combinational logic using MSI and LSI components with these questions:
- Differentiate between Multiplexer and demultiplexer. (Year: 2070, Group B, Marks: 5)
- Explain the full subtractor using decoder. (Year: 2070, Group A, Marks: 10)
- Explain the decoder and design with universal gates. (Year: 2070, Group B, Marks: 5)
- What is demultiplexer? Draw its block diagram and explain its working principle. (Year: 2071, Group A, Marks: 10)
- Draw a 3 to 8 decoder circuit and explain its operation. (Year: 2071, Group B, Marks: 5)
- Explain the PLA (Programmable Logic Array). (Year: 2071, Group B, Marks: 5)
- Draw a logic circuit of 8*1 multiplexer. (Year: 2073, Group B, Marks: 5)
- What do you mean by decoder? Design a 3 to 8 line decoder using 2 to 4 line decoder and explain it. (Year: 2073, Group A, Marks: 10)
- Explain the PLA with the block diagram. (Year: 2073, Group B, Marks: 5)
- Draw a block diagram, truth table, and logic circuit of 1*16 Demultiplexer and explain its working principle. (Year: 2074, Group A, Marks: 10)
- Design a 5x32 decoder with four 3x8 decoders with enable and one 2x4 decoder. Use block diagrams only. (Year: 2074, Group B, Marks: 5)
- Design and explain the Decimal adder with truth table and suitable diagram. (Year: 2074, Group B, Marks: 5)
- Implement the following function F = Σ(0,3,5,6,7) using:
- Decoder
- Multiplexer
- PLA
- Differentiate between PAL and PLA. (Year: 2074, Group A, Marks: 10; 2078, Group B, Marks: 5)
- Design the 4-bit parallel binary adder. (Year: 2073, Group B, Marks: 5)
- Implement the following function F = Σ(1,2,3,4,8) using:
- Decoder
- Multiplexer
- PLA
- Design the priority encoder circuit. (Year: 2075, Group B, Marks: 5)
- Implement half adder using 2-4 decoder. (Year: 2075, Group B, Marks: 5)
- Tabulate the PAL programming table for a 3-input, 4-output combinational circuit and mark the fuses to be blown in a PAL diagram. (Year: 2075, Group A, Marks: 10)
- Implement the following functions using PLA: w(A,B,C,D) = Σ(2,12,13) x(A,B,C,D) = Σ(7,8,9,10,11,12,13,14,15) y(A,B,C,D) = Σ(0,2,3,4,5,6,7,8,10,11,15) z(A,B,C,D) = Σ(1,2,8,12,13) (Year: 2077, Group A, Marks: 10)
- Implement F = Σ(0,2,3,4,7) using:
- Multiplexer
- Decoder
- PLA
- Implement the Boolean function F(P,Q,R,S) = Σ(3,4,6,8,9,14) using:
- 8 to 1 multiplexer
- PLA
- Decoder
- What is decoder circuit? Design 3 to 8 decoder circuit. (Year: 2080, Group B, Marks: 5; 2081, Group B, Marks: 5)
- Write short notes on: Encoder (Year: 2080, Group B, Marks: 5; 2081, Group B, Marks: 5)
- What is Multiplexer? Design 8 to 1 Multiplexer with low-level Multiplexers. (Year: 2081, Group B, Marks: 5)
Chapter 6: Synchronous and Asynchronous Sequential Logic
Delve into sequential logic with these past questions on flip-flops and sequential circuit design:
- What do you mean by clocked RS flip-flop? Explain. (Year: 2070, Group B, Marks: 5)
- How JK flip flop can convert into a D-flip flop? (Year: 2071, Group B, Marks: 5)
- Design a master-slave S-R flip flop with logic diagram and truth table. (Year: 2072, Group A, Marks: 10)
- How does a J-K flip flop differ from an S-R flip flop in its basic operations? Explain. (Year: 2072, Group B, Marks: 5)
- Explain the design procedure of sequential circuits. (Year: 2073, Group A, Marks: 10)
- Explain the R-S flip flop with truth table. (Year: 2073, Group B, Marks: 5)
- Explain master slave J-K flipflop. (Year: 2074, Group B, Marks: 5)
- Design clocked sequential circuit of the following state diagram by using JK flip-flop. (Year: 2075, Group A, Marks: 10)
- Design sequential circuit specified by the following state diagram using T flip-flops. (Year: 2077, Group A, Marks: 10)
- Explain negative-edge triggered D flip flop with necessary logic diagram and truth table. (Year: 2077, Group B, Marks: 5)
- Design the sequential circuit with respect to the following state diagram using J-K flip flops. (Year: 2078, Group A, Marks: 10)
- What is the drawback of RS Flipflop? Explain D Flip Flop in detail with a logic diagram, characteristics table, and characteristics equation. (Year: 2080, Group B, Marks: 5)
- How race condition in JK flipflop can be resolved? Explain. (Year: 2080, Group B, Marks: 5)
- Explain state diagram, state table, state reduction, and state assignment with suitable example. (Year: 2081, Group B, Marks: 5)
- Write about D flip flop with necessary circuit, block diagram, characteristic table, and equation. (Year: 2081, Group B, Marks: 5)
Chapter 7: Registers and Counters
Understand registers and counters with these practice questions from previous years:
- What do you mean by ripple counters? Explain with timing diagram. (Year: 2070, Group A, Marks: 10)
- What do you mean by Ripple counters? (Year: 2070, Group B, Marks: 5)
- Mention the different types of shift register. (Year: 2070, Group B, Marks: 5)
- Design the mod-6 asynchronous counter and explain with truth table. (Year: 2071, Group A, Marks: 10)
- Mention the different types of shift register and explain. (Year: 2071, Group B, Marks: 5)
- What do you mean by synchronous counter? Explain with truth table. (Year: 2071, Group B, Marks: 5)
- Design and implement with logic diagram of synchronous 3-bit up-down counter using J-K flip flop. (Year: 2072, Group A, Marks: 10)
- Explain the serial-In, parallel-out shift register. (Year: 2072, Group B, Marks: 5)
- Differentiate between a counter and a shift register. (Year: 2072, Group B, Marks: 5)
- Design a counter as shown in the state diagram below. (Year: 2074, Group A, Marks: 10)
- Explain shift register with parallel load. Highlight its practical implications. (Year: 2074, Group B, Marks: 5)
- Design a 4-bit binary ripple counter with D flip-flops. (Year: 2075, Group B, Marks: 5)
- What is the difference between a serial and parallel transfer? Explain how to convert serial data to parallel and parallel data to serial. What type of register is needed? (Year: 2075, Group B, Marks: 5; 2077, Group B, Marks: 5)
- Illustrate the use of Binary ripple counter and BCD ripple counter. (Year: 2077, Group B, Marks: 5)
- Provide one example where shift right operation can be used. Explain parallel-in parallel-out register. (Year: 2078, Group B, Marks: 5)
- What are the practical implementations of up counter? Explain Binary ripple counter. (Year: 2078, Group B, Marks: 5)
- Differentiate between synchronous and asynchronous counter. Design mode-7 synchronous counter using T-flip flop. Show necessary truth tables and k-maps. (Year: 2078, Group A, Marks: 10)
- What is shift register? Explain 4-bit SISO and PIPO with timing diagram. (Year: 2080, Group B, Marks: 5)
- Design an asynchronous mod 11 up counter using T flip flop. (Year: 2080, Group B, Marks: 5)
- What is asynchronous counter? Design asynchronous counter that counts the sequence of 0-1-4-6-7 using T flip-flop. (Year: 2080, Group A, Marks: 10)
- Differentiate between synchronous and asynchronous counter. Design a 3-bit synchronous binary counter using T Flip Flop. Draw its timing diagram. (Year: 2081, Group A, Marks: 10)
- Mention different types of shift registers. Explain SIPO with timing diagram. (Year: 2081, Group B, Marks: 5)
- Design a 2-bit asynchronous binary counter using T flip flop. Draw its timing diagram. (Year: 2081, Group B, Marks: 5)
Additional Questions (General/Supplementary Topics)
Don't forget to review these general topics for a comprehensive preparation:
- Write short notes on: Digital systems (Year: 2070, Group B, Marks: 5)
- Write short notes on: SIMM (Year: 2075, Group B, Marks: 5)
- Write short notes on: Parity Checker (Year: 2075, Group B, Marks: 5)
- Write short notes on: EBCDIC (Year: 2078, Group B, Marks: 5)
- Write short notes on: Parallel Adder (Year: 2080, Group B, Marks: 5)
We hope this chapter-wise question compilation is a valuable resource for your Digital Logic exam preparation. Good luck with your studies!